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ISL58214
Pin Configuration
ISL58214
(28 LD QFN)
TOP VIEW
Ordering Information
PART PACKAGE
NUMBER PART Tape & Reel
(Notes 1, 2, 3) MARKING (Pb-free)
PKG.
DWG. #
ISL58214CRZ-T13
58214 CRZ
28 Ld QFN
L28.4x5A
ISL58214CRZ-EVAL
Evaluation Board
D2 1
D3 2
D4 3
22 SEN
21 ENA
20 VSO
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
D5 4
D6 5
D7 6
D8 7
D9 8
THERMAL
PAD
19 ISRC
18 GND
17 VSO
16 VSO
15 ISNK
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL58214 . For more information on MSL please see
Pin Descriptions
PIN #
27, 28, 1, 2, 3, 4,
5, 6, 7, 8
9
10
PIN NAME
D0, D1, D2, D3,
D4, D5, D6, D7,
D8, D9
RFREQ
Ith
I/O
Input
Input
Input
PIN TYPE
Digital
Analog
Analog
PIN DESCRIPTION
These inputs specify the color current. I COLOR = Imax (512*D9 + 256*D8 + ... 4*D2
+ 2*D1 + D0). Imax is set by the scale DAC register (Page 0, Addr 15h), I SLOPE , and
RSET.
The resistor to GND sets the reference for the HFM (anti-speckle) oscillator.
Current into this pin becomes laser Threshold current; it has a 1000 ? input
impedance. The gain is programmable.
11
12, 14, 18
13
15
16, 17, 20
19
21
ISLOPE
GND
RSET
ISNK
VSO
ISRC
ENA
Input
GND
Input
Output
Power
Output
Input
Analog
GND
Analog
Analog
Power
Analog
Digital
Current into this pin sets the full scale DAC amplitude
Ground (connect all)
RSET to GND is the reference for the current DAC.
Floating laser diode output. Laser anode tied to a high supply.
The +5V power for the output drivers (connect all)
The output current into a grounded anode laser diode
When high the chip is enabled. When low, the chip is powered down and the outputs
disabled.
22
23
24
25
26
-
SEN
SDIO
SCLK
CLK
LOWP
PD
Input
I/O
Input
Input
Input
Power
Digital
Digital
Digital
Digital
Digital
Analog
The enable for the serial port.
The data for the serial port
Serial clock for SDIO data
The Dn data is clocked in on the rising edge of CLK
When high the output is disable for laser safety
The thermal pad must be heavily grounded as a heat sink.
NOTE: Pins with the same name are internally connected together; however, LDD pins must not be used for connecting together external components or
features.
3
FN6944.1
July 29, 2013
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